1. Field of the Invention
Embodiments of the present invention generally relate to semiconductor processing, and more specifically, to methods for fabricating dielectric materials on a substrate.
2. Description of the Related Art
Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. A CMOS transistor comprises a gate structure disposed between source and drain regions that are formed in the substrate. The gate structure generally comprises a gate electrode and a gate dielectric layer. The gate electrode is disposed over the gate dielectric layer to control a flow of charge carriers in a channel region formed between the drain and source regions beneath the gate dielectric layer.
Some exemplary applications of CMOS transistors include logic and flash memory applications. In such applications, gate stacks may have varying gate electrode over gate dielectric structures, such as SONOS, SANOS, TANOS, or the like. For example, SONOS stacks include layers, from top to bottom, of silicon (or polysilicon), silicon oxide, silicon nitride, silicon oxide, and silicon; SANOS stacks include layers, from top to bottom, of silicon (or polysilicon), aluminum oxide, silicon nitride, silicon oxide, and silicon; and TANOS stacks include layers, from top to bottom, of tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, and silicon.
In each of the above applications, a silicon nitride layer is formed over a silicon oxide layer. The silicon nitride layer may be formed by such techniques as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. However, CVD processes typically result in poor roughness of the surface, leading to process and or device performance variability. In addition, ALD processes typically have deposition initiation and incubation problems, resulting in poor film quality, reduced initial deposition rates, and high process variability.
Therefore, there is a need for an improved method of forming gate dielectric layers on a substrate for field effect transistors.